Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, the user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded hardware, or other types of resources) and interconnections available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs may then be determined to generate configuration data for the particular PLDs.
The generated configuration data (also referred to as original configuration data) is loaded into configuration memory of the PLDs to implement the programmable logic gates, LUTs, embedded hardware, and/or other types of configurable resources. The configuration memory of the PLDs may be volatile memory, such as random access memory (RAM). Once the configuration data is loaded into the PLDs, the configuration memory is essentially read-only memory that cannot be changed by the user.
Some of the configuration memory is allocated for distributed RAM (also known as non-configuration memory or distributed memory). After the PLD is configured, the portions of the configuration memory allocated for distributed RAM are usable for storing non-configuration data, such as user data. In this regard, the distributed RAM includes memory cells that may be used to store non-configuration data during operation of the PLD.
However, the configuration data in the configuration memory, like other types of memory, can suffer from soft errors. In this regard, even though the memory can be constructed correctly, events such as cosmic rays, alpha particle absorption, and/or other types of radiation can change a bit value stored in a memory cell, which may be referred to as a soft error. In some cases, the configuration data stored in the configuration memory can be repeatedly retrieved (e.g., read out) and compared to the original configuration data to facilitate detection of soft error events during device operation. However, when some of the configuration memory is used as distributed RAM for storing non-configuration data (e.g., user data), values stored by the distributed RAM are not predetermined by the original configuration data. As a result, the non-configuration data values may be incorrectly identified as errors when read out with the remaining configuration data and compared with the original configuration data (e.g., and/or through a cyclic redundancy check (CRC) or parity check).
Conventional approaches for facilitating compatibility between allocating distributed RAM and performing error detection generally require additional circuitry for each potential distributed RAM cell. In these approaches, additional circuitry are employed for each of these memory cells to block/prevent read out of these memory cells, e.g. during error detection. Often times the additional circuitry may require three or more transistors to be provided for each memory cell. In a conventional six transistor static RAM (SRAM) cell, the additional circuitry increases the overall transistor count and corresponding device area by at least 50% per memory cell. Therefore, there is a need to provide improved ways to facilitate deterministic read back and error detection for PLDs with potential distributed RAM.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.